Digital demodulator

ABSTRACT

A digital demodulator which will need no absolute phasing circuit is provided. A known-pattern BPSK signal generating circuit  6  generates the same known-pattern BPSK signal as a known-pattern BPSK signal in a received digital modulated wave in synchronism with the known-pattern BPSK signal in the received digital modulated wave, a carrier-reproducing phase error detecting circuit  7  has a phase error table where one of reference phases in a signal point position of a demodulation baseband signal is made a convergence point, a phase error voltage corresponding to a phase error between a phase determined from the signal point position of the demodulation baseband signals and a phase convergence point is sent out, by enable-controlling a carrier-reproducing loop filter  8  according to the known-pattern BPSK signal outputted from the known-pattern BPSK signal generating circuit  6 , the phase error voltage is smoothed, and carrier reproduction is performed while controlling the frequency of a reproduced carrier according to the smoothed output so that the phase in the signal point position coincides with the phase convergence point.

This application is a 371 of PCT/JP99/00400, filed on Jan. 29, 1999.

TECHNICAL FIELD

The present invention relates to a digital demodulator for a digitalbroadcasting receiver that receives BS digital broadcasting, and furtherin particular relates to a digital demodulator for a digitalbroadcasting receiver that receives digital modulated waves in whichmodulated waves as a result of a plurality of modulation systems withrespectively different necessary C/N (the ratio of carrier power tonoise power) values undergo time-base-multiplexing for transmission.

BACKGROUND ART

In the BS digital broadcasting system, when the digital modulated waves,for example, 8PSK modulated waves, QPSK modulated waves, and BPSKmodulated waves all being the primary signals, which are transmitted ina plurality of modulation systems with different necessary C/N values,are combined every specific interval, and are added to the hierarchicaltransmission system in which transmission takes place repeatedly on aframe-by-frame basis, a system in which burst symbol signals enablingreception with a low C/N value are inserted is adopted. The burst symbolsignals are signals having undergone BPSK modulation in the known PNcodes.

Moreover, in such a hierarchical modulation system, the framesynchronization pattern as well as the superframe discrimination signalsare also patterned in a predetermined fashion and have undergone BPSKmodulation. In addition, in a digital broadcasting receiver, absolutephasing, which makes reception phases correspond to phases at thetransmitting party, is implemented in a digital demodulator for thepurpose of decoding or the like with a decoder of demodulation basebandsignals. Therefore, in the hierarchical modulation system, framesynchronization signals, the later-described TMCC signals fortransmission multiplexed configuration discrimination, and burst symbolsignals undergo BPSK demodulation, and from the reception phases of thereceived frame synchronization pattern (the absolute phase reception,and the inverse phase reception), absolute phasing is performed.

However, at the time of integration of a digital demodulator, there wasa problem that the required area of the digital demodulator is increaseddue to an absolute phasing circuit.

The purpose of the present invention is to provide a digital demodulatorneeding no absolute phasing circuit.

DISCLOSURE OF THE INVENTION

According to the present invention, the digital demodulator of areceiver for digital broadcasting which receives and transmits digitalmodulated waves created by time-base-multiplexing waves modulated by aplurality of modulation systems comprises known-pattern signalgenerating means for generating in synchronism with known-patternsignals in the received digital modulated waves the same known-patternsignal as a known-pattern BPSK signal in the received digital modulatedwaves, carrier-reproducing phase error detecting means, which comprisesa phase error table having one reference phase as a convergence pointbetween two reference phases of signal point positions of BPSKdemodulation baseband signals, for sending out a phase error outputbased on a phase error between the phase obtained from the signal pointposition of the demodulation baseband signals and the phase convergencepoint, and a carrier-reproducing loop filter which is controlled forenablement based on the known-pattern signals outputted from theknown-pattern signal generating means and smoothes the phase erroroutputs during an enabling period, wherein carrier reproduction isimplemented by controlling the frequency of a reproduced carrier so thatbased on the output of the carrier-reproducing loop filter, the phase ofthe above described signal point position coincides with the phaseconvergence point.

In the digital demodulator according to the present invention, the sameknown-pattern signal as the known-pattern BPSK signal in the receiveddigital modulated waves is generated in synchronism with theknown-pattern BPSK signals in the received digital modulated waves fromknown-pattern signal generating means, the phase error output based onthe phase error between the phase obtained from the signal pointposition of the demodulation baseband signals and the phase convergencepoint is detected from carrier-reproducing phase error detecting meanscomprising only the phase error table having one reference phase as theconvergence point between the reference phases of the signal pointpositions of the BPSK demodulation baseband signal as the phase errortable, for the purpose of phase error detection, and beingenable-controlled based on the known-pattern BPSK signals outputted fromthe known-pattern signal generating means, the phase error outputsduring the enabling period are smoothed by a carrier-reproducing loopfilter, and carrier reproduction is implemented by controlling thefrequency of the reproduced carrier so that based on the output of thecarrier-reproducing loop filter, the phase of the above described signalpoint position coincides with the phase convergence point, and thereforesince the phase point of the reception signal converges to the absolutephase, the reception signal undergoes absolute phasing and no absolutephasing circuit will be needed.

The digital demodulator according to the present invention goes wellwith only one phase error table, and for the period of such aknown-pattern BPSK signal potential that will not enable thecarrier-reproducing loop filter, for the period of TMCC, for the periodof primary signal BPSK signal, for the period of QPSK signal, and forthe period of 8PSK signal, a filter operation is halted, and therefore,the phases obtained from the signal point positions of the demodulationbaseband signals for the period of such a known-pattern BPSK signalpotential that will not enable the carrier-reproducing loop filter, forthe period of TMCC, for the period of primary signal BPSK signal, forthe period of QPSK signal, and for the period of 8PSK signal arecompared with the reference phases in the phase error table so that thephase error output is sent out, but during this period thecarrier-reproducing loop filter will be halting its operation, givingrise to no inconveniences.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the configuration of a digitaldemodulator according to an embodiment of the present invention;

FIGS. 2(a)-2(g) show a block diagram of the frame of signals to besupplied to the digital demodulator according to the embodiment of thepresent invention and shows waveforms of the signals Rs, A1, A0, As, Bs,and SF;

FIG. 3 is a block diagram showing the configuration of an arithmeticcircuit as well as numerical control oscillator in the digitaldemodulator according to the embodiment of the present invention;

FIGS. 4(a) and 4(b) are an explanatory diagram showing a superframediscrimination pattern in signal frame to be supplied to the digitaldemodulator according to the embodiment of the present invention; and

FIGS. 5(a) and 5(b) are an explanatory graphs on a phase error table inthe digital demodulator according to the embodiment of the presentinvention.

EMBODIMENT OF THE INVENTION

The digital demodulator according to the present invention will bedescribed by way of the embodiment as follows.

FIG. 1 is a block diagram showing the configuration of a digitaldemodulator according to the embodiment of the present invention.

Prior to explanation of the digital demodulator according to theembodiment of the present invention, the frame configuration of ahierarchical modulation system will be described. FIG. 2(a) is a diagramshowing an example of the frame configuration of a hierarchicalmodulation system. One frame is configured by one header portion 192symbol, and 39936 symbols formed with a pair consisting of a pluralityof 203 symbols and 4 symbols.

Further in particular, the frame configuration is formed in the order offrame synchronization pattern (BPSK) 32 symbols (within whichpredetermined 20 symbols are used) configuring a header, TMCC(Transmission and Multiplexing Configuration Control) pattern (BPSK) 128symbols for transmission multiplexed configuration discrimination aswell as superframe discrimination information pattern 32 symbols (withinwhich predetermined 20 symbols are used), primary signals (TC8PSK) 203symbols succeeding the header, burst symbol signals (which are indicatedas BS in FIG. 2(a)) 4 symbols undergoing BPSK modulation with pseudorandom signals to be set every 1 frame period, primary signals (TC8PSK)203 symbols, burst symbol signals 4 symbols, . . . , primary signals(QPSK) 203 symbols, burst symbols signals 4 symbols, primary signals(BPSK) 203 symbols, and burst symbols signals 4 symbols. Here, 8 framesare called as a superframe, and the superframe discriminationinformation pattern is information for superframe discrimination.

Now, description of the digital demodulator according to the embodimentof the present invention shown in FIG. 1 will be resumed. The digitaldemodulator according to the embodiment of the present inventioncomprises an arithmetic circuit 1, a numerical control oscillator (NCO)2, a rolloff filter 3 comprising a digital filter and showing a raisedcosine characteristic, a frame synchronization timing circuit 4, atransmission mode judging circuit 5, a known-pattern signal generatingcircuit 6 generating the known-pattern BPSK signals in synchronism withthe frame leader, a carrier-reproducing phase error detecting circuit 7having a phase error table for carrier reproduction and sending out aphase error voltage for carrier reproduction corresponding to ademodulation baseband signal outputted from the rolloff filter 3, acarrier-reproducing loop filter 8 comprising a low bus digital filterwhich is selectively enabled by an output from the known-pattern signalgenerating circuit 6 and smoothes the phase error voltage, and an AFCcircuit 9 sending out the AFC signals to the numerical controloscillator 2 based on the output from the carrier-reproducing loopfilter 8.

The numerical control oscillator 2 comprises, as shown in FIG. 3, a sinewave table 23 outputting the sine wave data 23 a and 23 b havingmutually opposite polarity and a cosine wave table 24 outputting thecosine wave data 24 a and 24 b, and based on outputs from the AFCcircuit 9 outputs sine wave data 23 a and 23 b as well as cosine wavedata 24 a and 24 b each having mutually opposite polarity and incooperation with the AFC circuit 9 outputs sine wave signals as well ascosine wave signals having mutually opposite polarity substantiallyforming the reproduced carrier.

The arithmetic circuit 1 comprises, as shown in FIG. 3, a multiplier 1 amultiplying the baseband signals i, which have been quasi-synchronouslydetected in the I axis, by the sine wave data 23 a, a multiplier 1 bmultiplying the baseband signals i by the cosine data 24 a, a multiplier1 d multiplying baseband signals q, which have been quasi-synchronouslydetected in the Q axis, by the sine wave data 23 b having an oppositepolarity, a multiplier 1 e multiplying the baseband signals q by thecosine wave data 24 b, an adder 1 c adding an output of the multiplier 1b to an output of the multiplier 1 d and outputs the result as abaseband signal 1, and an adder 1 f adding an output of the multiplier 1a to an output of the multiplier 1 e and outputs the result as abaseband signal Q, and in receipt of the output from the numericalcontrol oscillator 2, causes the baseband signals i and q to undergofrequency synchronization, and sends out respectively to the rollofffilter 3 the baseband signals I and Q being frequency-synchronizedoutputs.

The frame synchronization timing circuit 4 receives the baseband signalsID and QD outputted from the rolloff filter 3, and sends out the TMCCpattern to the transmission mode judging circuit 5. Based on the decodedresults of the TMCC patterns, the transmission mode judging circuit 5sends out the two-bit transmission mode signals to the framesynchronization timing circuit 4, corresponding to 8PSK signals(demodulated outputs having undergone demodulation on the 8PSK modulatedwaves are indicated as 8PSK signals) being high hierarchical signals,QPSK signals (demodulated outputs having undergone demodulation on theQPSK modulated waves are indicated as QPSK signals) being lowhierarchical signals, and BPSK signals (demodulated outputs havingundergone demodulation on the BPSK modulated waves are indicated as BPSKsignals).

The frame synchronization timing circuit 4 receives the baseband signalsID and QD and detects the frame synchronization pattern to output theframe synchronization signals FSYNC to the AFC circuit 9 and to causethe AFC circuit 9 to perform an AFC operation on a frame-by-frame basis,and in receipt of the transmission mode signals being outputted from thetransmission mode judging circuit 5, outputs the signal Rs shown in FIG.2(b) in synchronism with the frame synchronization pattern leader, andimplements processing on the signal A1 shown in FIG. 2(c) having a highpotential during the BPSK signal period, the frame synchronizationpattern interval, the superframe discrimination pattern interval, andthe burst symbol signal interval and the signal A0 shown in FIG. 2(d)having a high potential during the QPSK signal period, and outputs thesignal As shown in FIG. 2(e) having high potential during the framesynchronization pattern period, the signal Bs shown in FIG. 2(f) havinghigh potential during the burst symbol signal period, and the signal SFshown in FIG. 2(g) having high potential during the superframediscrimination pattern period.

Next, the superframe discrimination pattern will be described. FIG. 4(a)is an explanatory diagram of the superframe discrimination pattern, andW₁ indicates a frame synchronization pattern, which is same for allframes. In FIG. 4(a), the patterns W₂ and W₃ indicate the superframediscrimination pattern, and the frame synchronization pattern as well asthe superframe discrimination pattern are extracted from each frame fordescription. For the leading frame, the superframe discriminationpattern is the W₂ pattern, and for the superframe discriminationpatterns on all of seven frames from the second frame through the eighthframe are W₃, and the pattern W₃ is formed as an inverted pattern of W₂.

The frame synchronization timing circuit 4 outputs, as shown in FIG.4(b), the superframe discrimination pattern discriminating signals witha low potential during the superframe discrimination pattern W₂ periodof the leading frame, being the signals to discriminate the superframediscrimination pattern being a high potential during the superframediscrimination pattern W₃ period of the succeeding seven frames.

The known-pattern signal generating circuit 6 comprises the framesynchronization pattern generating circuit 61, the superframediscrimination pattern generating circuit 62, the burst symbol patterngenerating circuit 63, the exclusive OR circuit 64, the inverters 65 and66, and the OR gate circuit 67, and outputs from the OR gate circuit 67the known-pattern signals to the carrier-reproducing loop filter 8 asthe enabling signals.

The frame synchronization pattern generating circuit 61 is reset by thesignal Rs, and receives the signal As, that is, the signal during theframe synchronization pattern period as an enabling signal, and sendsout a signal configuring the frame synchronization pattern insynchronism with the bit clock signals. This signal is inverted in theinverter 65, and the inverted signals are sent out to thecarrier-reproducing loop filter 8 as enabling signals via the OR gatecircuit 67. For example, at a high potential, enabling will beinstructed.

The superframe discrimination pattern generating circuit 62 is reset bythe signal Rs, and receives the signal SF, that is, the signal duringthe superframe discrimination pattern period as an enabling signal, andsends out in succession to the exclusive OR circuit 64 the superframediscrimination pattern W₂ configuring the leading frame in synchronismwith the bit clock signals. This signal undergoes an exclusive ORoperation with the superframe discrimination pattern discriminatingsignals outputted from the frame synchronization timing circuit 4, andundergoes inversion and is sent out to the OR gate circuit 67.

Accordingly, by the superframe discrimination pattern discriminatingsignals outputted from the superframe discrimination pattern generatingcircuit 62, the superframe discrimination pattern of W₂ for the leadingframe and the pattern W₃, which has undergone inversion on the patternW₂ for the succeeding seven frames, are sent out from the exclusive ORcircuit 64. As a result of this, from the exclusive OR circuit 64, thesignals W₂, W₃, W₃, W₃, W₃, W₃, W₃, and W₃ of the superframediscrimination pattern as shown in FIG. 4(a) are sent out to thecarrier-reproducing loop filter 8 as the enabling signals on aframe-by-frame basis from the leading frame through the eighth frame viathe OR gate circuit 67. For example, at a high potential, enabling willbe instructed.

The burst symbol pattern generating circuit 63 is reset by the signalRs, and receives the signal Bs, that is, the signal during the burstsymbol pattern period as an enabling signal, and sends out in successionin synchronism with the bit clock signals to the inverter 66 the burstsymbol signals, which undergo inversion in the inverter 66 to be sentout. This inverted signals are sent out as enabling signals via the ORgate circuit 67. For example, at a high potential, enabling will beinstructed.

As a result of this, the known-pattern signal generating circuit 6 willenable the carrier-reproducing loop filter 8 during the period of highpotential of the inverted signal of the frame synchronization pattern,the inverted signal of the superframe discrimination pattern shown inFIG. 4(a) corresponding to the frame numbers on a frame-by-frame basis,and the inverted signal of the burst symbol signals.

In receipt of the baseband signals ID and QD outputted from the rollofffilter 3, the carrier-reproducing phase error detecting circuit 7detects the phase error between the phase of one of the phase basebandsignals ID and QD and its reference phase. Herein, the phase basesignals ID and QD are obtained from the signal point position based onthe baseband signals ID and QD with reference to the carrier-reproducingphase error table, and sends out the phase error voltage values based onthe phase error.

Further in particular, the carrier-reproducing phase error detectingcircuit 7 comprises the carrier-reproducing phase error table shown inFIG. 5(a) having the phase convergence point (0(2π) radian) of one ofthe reference phases of the baseband signals ID and QD, and obtains thephases from the signal point positions of the baseband signals ID andQD, and the phase error voltage based on the phase error between saidphase and one of the reference phases is obtained from thecarrier-reproducing phase error table, and is sent to thecarrier-reproducing loop filter 8.

Then, when phases obtained from the signal point position of thebaseband signals ID and QD inputted to the carrier-reproducing phaseerror detecting circuit 7 are those which are in an increasing directionfrom not less than π radian to not more than 0 (2π) radian, a negativephase error voltage value shown in FIGS. 5(a) and 5(b) is outputted andphases are those which are in a decreasing direction from less than πradian to 0 (2π) radian, a positive phase error voltage value shown inFIGS. 5(a) and 5(b) is inputted, and under control of the AFC circuit 9(carrier-generating loop) to which this phase error voltage is supplied,the phases having been obtained from the signal point positions undergoas shown in FIG. 5(b) convergence to 0 (2π) radian. In this case, thephase error voltage value takes maximum value in the+ (positive)direction and maximum value in the − (negative) direction when the phaseis π radian.

The phase error voltage having been outputted from thecarrier-reproducing phase error detecting circuit 7 based on the phaseshaving been obtained from the signal point positions of the basebandsignals ID and QD is supplied to the carrier-reproducing loop filter 8comprising a digital low-pass filter, and the phase error voltage issmoothed. In this case, the signals to be outputted from theknown-pattern signal generating circuit 6 are supplied to thecarrier-reproducing loop filter 8 as enabling signals (CRFLGP), thecarrier reproducing loop filter 8 performs a filter operation onlyduring the period of the bit “0” (a low potential) for the period of theframe synchronization pattern, the period of the superframediscrimination pattern, and the period of the burst symbol signal.During the period of bit “1” (high potential) where the bit “0” has beeninverted, the carrier-reproducing loop filter 8 is enabled as havingbeen described so far.

During the period of the bit “1” for the period of the framesynchronization pattern, the period of the superframe discriminationpattern, the period of the burst symbol signal, the period of the BPSKsignal of the primary signal, the period of the QPSK signal, and theperiod of the 8PSK signal, the carrier-reproducing loop filter 8 isdisenabled to halt an operation and is caused to keep the filter outputat the time when the filer has operated just before the halting. Theoutput from the carrier-reproducing loop filter 8 is supplied as thetuning voltage of carrier-reproducing loop to the AFC circuit 9.

On the other hand, the phase reference point of the signal pointpositions of the baseband signals ID and QD outputted from the rollofffilter 3 is two of 0 (2π) radian, or π radian. However, the phasereference point of the carrier-reproducing phase error detecting tablewhich the carrier-reproducing phase error detecting circuit 7 comprisesis 0 (2π) radian. Accordingly, the phase error voltage based on a phaseerror between phases of signal point positions of the baseband signalsID and QD outputted from the rolloff filter 3 and the reference point 0(2π) radian is obtained, but the phase error voltage based on a phaseerror between phases of signal point positions of the baseband signalsID and QD and the reference point π radian is not obtained.

Nevertheless, if the baseband signal with the phase reference point ofthe signal point position being in the value of π radian is supplied tothe carrier-reproducing phase error detecting circuit 7, or if thebaseband signal based on the BPSK signal, the QPSK signal, and the 8PSKsignal of the primary signal is supplied to the carrier-reproducingphase error detecting circuit 7, in these cases, no inconvenience willtake place since the carrier-reproducing loop filter 8 will not beenabled as described above.

Operation of the digital demodulator according to an embodiment of thepresent invention described above will be described.

In a BS digital broadcasting receiver, desired signals within agenerally designated channel undergo scanning with a scanning operationof the AFC circuit 10, and undergo operation so that the carrier iscaptured. In the digital demodulator according to an embodiment of thepresent invention, in receipt of the desired signals, which undergoorthogonal demodulation with the quasi-synchronous detecting system, thedemodulation baseband signals i and q, which are supplied to thearithmetic circuit 1, as well as output data from the numericalcontrolling oscillator 2 undergo an arithmetic operation, and areconverted into the baseband signals I and Q.

The baseband signals I and Q are supplied to the rolloff filter 3, andthe baseband signals ID and QD via the rolloff filter 3 are supplied tothe carrier-reproducing phase error detecting circuit 7, and the phaseerror voltage for carrier reproduction based on the phases obtained fromthe signal point positions based on the baseband signals ID and QD isobtained, and then the phase error voltage is smoothed by thecarrier-reproducing loop filter 8 and is supplied to the AFC circuit 9as the tuning voltage of the carrier-reproducing loop, and the output ofthe AFC circuit 9 is given to the numerical controlling oscillator 2,and the carrier frequency is controlled so that the phase error voltagebecomes 0, and thus carrier reproduction is implemented.

On the other hand, the baseband signals ID and QD are supplied to theframe synchronization timing circuit 4, and the frame synchronizationpattern is detected, and thus the frame synchronization is captured toestablish the frame timing, then time-series positions respectively ofthe frame synchronization pattern, the TMCC pattern, the superframediscrimination pattern, and the burst symbol signal are clarified, andthe TMCC pattern is sent out to the transmission mode judging circuit 5to undergo decoding, and in receipt of the transmission mode signaloutputted from the transmission mode judging circuit 5, the framesynchronization timing circuit 4 sends out the signals Rs, As, which isgenerated from A1 and A0, Bs and SF.

In receipt of the signals Rs, As, Bs, SF, and the superframediscrimination pattern signals sent out from the frame synchronizationtiming circuit 4, the signals with high potential based on the receptionphase point in which the reception phase points on a time unit basishave been respectively recognized from the reception phases as well asthe positions in terms of time based on the inverted signals of theframe synchronization pattern signals, the superframe discriminationpattern signals, and the burst symbol signals, and the reception phasepoint has been recognized is sent out from the known-pattern signalgenerating circuit 6 to the carrier-reproducing loop filter 8 as theenabling signals.

And on the other hand, in the carrier-reproducing phase error detectingcircuit 7 which is supplied with the baseband signals ID and QDoutputted from the rolloff filter 3, the phase error voltage based onthe difference between the phase obtained from the signal point positionof the baseband signals ID and QD the convergence point 0 (2π) radian ofthe phase error table is obtained from the phase error table shown inFIG. 5, and is sent out to the carrier-reproducing loop filter 8.

Under this condition, from the known-pattern signal generating circuit6, the inverted signal of the frame synchronization pattern, theinverted signal of the superframe discrimination pattern, and theinverted signal of the burst symbol signal are supplied to thecarrier-reproducing loop filter 8 as the enabling signals (CRFLGP), andduring the period for high potential of the enabling signals (CRFLGP),the phase error voltage is smoothed with the carrier-reproducing loopfilter 8, and the output from the carrier-reproducing loop filter 8 issent out to the AFC circuit 9, and based on the output from thecarrier-reproducing loop filter 8, frequency control of the carrier isimplemented, and carrier reproduction by burst reception is implemented.

For the period when the inverted signal of the frame synchronizationpattern, the inverted signal of the superframe discrimination pattern,and the inverted signal of the burst symbol signal remains in a lowpotential, for the period of the primary signal BPSK signal, for theperiod of the QPSK signal, and for the period of 8PSK signal, theenabling signal (CRFLGP) remains in a low potential, and for the periodof a low potential, the carrier-reproducing loop filter 8 is disenabledto halt an operation and is caused to keep the filter output status atthe time when the filer has operated just before the halting, andcarrier reproduction is implemented.

As described above, in the digital demodulator according to anembodiment of the present invention, based on the phase error voltageobtained by the phase error table with one convergence point, carrierreproduction is implemented, and since the phase point of the receptionsignal converges into one phase point, the reception signal undergoesabsolute phasing and no absolute phasing circuit will be needed. As aresult of this, a required area when the digital demodulator undergoescircuitry integration will be made less.

Incidentally, also when the low potential signal among the invertedsignal of the frame synchronization pattern, the inverted signals of thesuperframe discrimination pattern as well as the inverted signals of theburst symbol signals, and the baseband signals ID and QD based on theBPSK signal, QPSK signal, and the 8PSK signal of the primary signal, theQPSK signal are supplied to the carrier-reproducing phase errordetecting circuit 7, the phase error voltage is detected with thecarrier-reproducing phase error table (see FIG. 5) of the referencepoint of 0 (2π), but in this case, the enabling signal (CRFLCP) remainsin a low potential, and since the carrier-reproducing loop filter 8 isnot enabled, giving rise to no problems as described before. Inaddition, as for a portion of the burst symbols, in some cases, somedata are sent out, but in that case, the interval where no data are sentout will be used.

Incidentally, in a mode of the above-described embodiment, comprising inthe carrier-reproducing phase error detecting circuit 7 a phase errortable with the phase convergence point being disposed at π radianinstead of the phase convergence point of 0 (2π) radian to detect thephase error voltage based on the phase error of the signal point phasebased on the demodulation baseband signals ID and QD, and beingconfigured so that in the known-pattern signal generating circuit 6 theinverters 65 and 66 are omitted and the output from the exclusive ORcircuit 64 is outputted without undergoing inversion, thecarrier-reproducing loop filter 8 may be arranged to be enabled with thebit “0” of the output from the known-pattern signal generating circuit6.

Industrial Applicability

As having been described so far, according to the digital demodulatoraccording to the present invention, at carrier-reproducing phase errordetection for the period of reception of the known-pattern BPSK signal,the phase error table with one convergence point is used to detect thephase error based on the reception phase of the reception signal, andthe carrier reproduction is implemented based on the phase error, andthus, the reception signal undergoes absolute phasing and no absolutephasing circuit will be needed, which gives rise to an advantage thatthe required area when the digital demodulator undergoes circuitryintegration will be made less.

What is claimed is:
 1. A digital demodulator of a receiver for digitalbroadcasting which receives and transmits digital modulated wavescreated by time-base-multiplexing waves modulated by a plurality ofmodulation systems, comprising: known-pattern signal generating meansfor generating in synchronism with known-pattern signals in receiveddigital modulated waves the same known-pattern signal as a known-patternBPSK signal in the received digital modulated waves; carrier-reproducingphase error detecting means, which comprises a phase error table havingone reference phase as a convergence point between two reference phasesof signal point positions of BPSK demodulation baseband signals, forsending out a phase error output based on a phase error between thephase obtained from the signal point position of the demodulationbaseband signals and the phase convergence point; and acarrier-reproducing loop filter which is controlled for enablement basedon the known-pattern signals outputted from the known-pattern signalgenerating means and smoothes the phase error outputs during an enablingperiod, wherein carrier reproduction is implemented by controlling thefrequency of a reproduced carrier so that, based on the output of thecarrier-reproducing loop filter, the phase of said signal point positioncoincides with the phase convergence point.
 2. The digital demodulatoraccording to claim 1, characterized in that the carrier-reproducing loopfilter is controlled to enablement for the period of low potential ofthe known-pattern signals outputted from the known-pattern signalgenerating means.